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Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory Adri`a Armejach?‡ ? Anurag Negi†
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Document Date: 2012-02-23 21:17:04

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Embedded Computer Systems / /

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Facility

Barcelona Supercomputing Center Universitat Polit`ecnica de Catalunya Chalmers University of Technology / /

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comparison between different systems / interconnection network / lazy versioning systems / 2D mesh network / computer systems / hybrid-policy hardware / parallel hardware / transactional applications / eager systems / eager-lazy hardware / adaptable hardware / eager and lazy conflict resolution systems / software intervention / lazy conflict resolution systems / out-of-order processors / version management / /

MarketIndex

STAMP / /

Organization

Universitat / Chalmers University of Technology / Stanford / /

Person

Cao Minh / J. D. Davis / L. Hammond / V / B. D. Carlstrom / M. Chen / C. C. Minh / B. Hertzberg / M. K. Prabhu / H. Volos / A. McDonald / V. Wong / H. Wijaya / B. D. Carlstrom / V / W. Baek / K. Olukotun / C. Kozyrakis / Osman S. Unsal / /

Position

representative / Cao / /

Product

Vizio L32 Television / /

ProvinceOrState

Pennsylvania / /

Technology

Alpha / shared memory system / out-of-order processors / Cache Memory / Simulation / SRAM / Parallel Processing / /

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