High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah)

First Page		Document Content
Date: 2015-10-02 08:07:40 Concurrency control Transaction processing Linearizability Non-blocking algorithm Lock Transactional memory Compare-and-swap Software transactional memory Transactional Synchronization Extensions		High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah) Add to Reading List Source URL: hpts.ws Download Document from Source Website File Size: 658,86 KB Share Document on Facebook

	Reagents: Expressing and Composing Fine-grained Concurrency Aaron Turon Northeastern University DocID: 1rk2P - View Document
	Exercise 10: Exercising in style Task 1: Very exclusive! a) Give a solution to mutual exclusion using a fetch-and-add register. b) Give a solution to mutual exclusion using a compare-and-swap register. c) Give a solution DocID: 1r8fM - View Document
	Semantically Enhanced Containers for Concurrent Real-Time Systems Damian Dechev1 , Peter Pirkelbauer1 , Nicolas Rouquette2 , and Bjarne Stroustrup1 , , . DocID: 1pDQ8 - View Document
	High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah) DocID: 1ppnX - View Document
	Lock-free Dynamically Resizable Arrays Damian Dechev, Peter Pirkelbauer, and Bjarne Stroustrup Texas A&M University College Station, TX {dechev, peter.pirkelbauer}@tamu.edu, DocID: 1p8Ow - View Document