First Page | Document Content | |
---|---|---|
Date: 2012-09-06 23:48:36Computer architecture Computing Computer hardware Computer memory Opteron Cell Multi-core processor Intel Core SPARC T5 Advanced Micro Devices Xeon CPU cache | Optimization of a Lattice Boltzmann Computation on State-of-the-Art Multicore Platforms Samuel Williams∗,a,b , Jonathan Cartera , Leonid Olikera , John Shalfa , Katherine Yelicka,b a CRD/NERSC, b CSAdd to Reading ListSource URL: crd.lbl.govDownload Document from Source WebsiteFile Size: 1,07 MBShare Document on Facebook |