Altera Corporation / Chip RAM System Interconnect Send Feedback Altera Corporation / System Interconnect Send Feedback Altera Corporation / /
Facility
port SDRAM L3 Interconnect Block Diagram / HPS bridge Three FPGA-to-SDRAM / The FPGA-to-HPS bridge / FPGA-toHPS Bridge / MPU Accelerator Coherency Port / Bridge DMA Observability Network L4 ECC Bus Slaves / /
IndustryTerm
on different clock domains and protocols / changes to any products / observability network / semiconductor products / throughput peripheral devices / /
OperatingSystem
L3 / /
Organization
U.S. Patent and Trademark Office / /
Person
Bus Slaves / /
Position
memory scheduler / SDRAM controller / DDR L3 Firewall DDR Firewall SDRAM Scheduler / ACP L4 MP / Contain DDR Scheduler / hard memory controller / Timer System Manager Reset Manager Clock Manager FPGA Manager / bit AXI SDRAM Scheduler / FPGA manager / Major / bit AXI Hard Memory Controller / Scheduler / Manager L3 CSR L4 Firewall CSR Altera Corporation L4 ECC Bus SD/MMC ECC / security support Dedicated SDRAM Scheduler / SDRAM hard memory controller / SDRAM scheduler / /
ProvinceOrState
California / /
Technology
semiconductor / FPGA / RAM / Firewall / firewall System / SDRAM / following protocols / UART / /
7 System Interconnect[removed]a10_54004