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Formal methods / Hardware verification languages / Property Specification Language / Accellera / Technical communication / Verilog / Specification / Functional verification / Functional specification / Electronic design automation / Electronic engineering / Hardware description languages


Property Specification Language Reference Manual Version 1.1 June 9, 2004
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Document Date: 2004-06-29 00:18:58


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File Size: 1,62 MB

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City

Napa / /

Company

M. Clarke Carnegie Mellon Ben Cohen / Inc Bernard Deadman SDV Inc / IBM Haifa Research Lab Tom Fitzpatrick Co-Design Automation Inc / Chen Verplex Systems Inc. / Motorola Inc. / Cadence Design Systems / Infineon Technologies / Co-Design Automation Inc. / Roy Armoni Intel Corp. / Harry Foster Jasper Design Automation Inc. / Sun Microsystems Adriana Maggiore AltraVerifica Ltd. / Verplex Systems Inc. / Cambridge John Havlicek Motorola Inc. / Accellera Organization Inc. / Gal Vardi Marvell Semiconductor Ltd / RTL / Yaron Kashai Verisity Design Inc. / Lab Christian Pichler Siemens Carl Pixley Synopsys Inc. / Ken Albin Motorola Inc. / TransEDA Technology Ltd / David Van Campenhout Verisity Design Inc. / Bassam Tabbara Novas Software Inc. / Joseph Lu Nvidia Inc. / In Design Automation Inc. / Johan MÃ¥rtensson Safelogic Anthony McIsaac STMicroelectronics Ltd. / Austin Andrea Fedeli STMicroelectronics Ltd. / /

Country

United States / /

/

Facility

Allen Emerson University of Texas / Ltd. Dana Fisman Weizmann Institute of Science / Inc. Sandeep K. Shukla University of California / Gordon University of Cambridge John Havlicek Motorola / /

IndustryTerm

verification tools / testbench automation tool / final product / simulation tool / bus protocol / /

Organization

IBM Haifa Research Lab / Technical Committees / University of Texas at Austin / Carnegie Mellon / Rice University / University of California / Irvine / Inc. Daniel Geist IBM Haifa Research Lab Vassilios Gerousis Infineon Technologies Michael J.C. Gordon University of Cambridge John Havlicek Motorola / Weizmann Institute of Science / /

Person

Moshe Y. Vardi / Cindy Eisner / Ambar Sarkar / Michael Siegel / Richard Ho / Bow-Yaw Wang / Andrew Seawright / Thomas L. Anderson / Jayaram Bhasker / Erich Marschner / Klaus Winkelmann / Johan Alfredsson Safelogic Thomas / Lynn Horobin / /

/

Position

design architect / Consultant / verification engineer / Co-Chair Group Chair Work Group / /

ProvinceOrState

Texas / California / /

Technology

Verilog / bus protocol / Finite State Machine / simulation / /

URL

www.eda.org/vfv / /

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