| Document Date: 2007-02-22 22:31:46
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City Lausanne / Austin / / Company John Wiley & Sons Ltd. / Cryptographic Hardware / Xilinx / the AES / Embedded Systems / / Continent Europe / / Country Switzerland / Belgium / United States / / / Event FDA Phase / / IndustryTerm lower hardware / eSTREAM web site / sensor networks / reconfigurable hardware / computerized applications / namely software / even software / Wireless Communications / sound solution / symmetric encryption algorithms / / NaturalFeature Introduction Stream / / Organization ASIC / US Federal Reserve / group of seven / U.S. Securities and Exchange Commission / IEEE Computer Society / / Person Jean-Jacques Quisquater / R. Blattmann / V / Philippe Bulens / Xavier Standaert / Field-Programmable Logic / / Position post doctoral researcher / designer / / Product Grain128 / / ProvinceOrState Texas / / Region Levant / Benelux / / Technology encryption / FPGA / cryptography / RAM / ASIC / Control Technologies / Information Technology / symmetric encryption algorithms / Wireless Communications / Fair Exchange Protocols / block cipher / http / Radio Frequency / secret key / VHDL / stream cipher / FPGA technologies / / URL http /
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FPGA Implementations of eSTREAM Phase-2 Focus Candidates with Hardware Profile Philippe Bulens⋆ , Kassem Kalach⋆⋆ , Fran¸cois-Xavier Standaert⋆ ⋆ ⋆ and Jean-Jacques Quisquater UCL Crypto Group, Universit´e