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Company VR / Hewlett Packard / Computer Sciences / Motorola / Embedded Software / VL / Mentor Graphics / Synopsys / / Country Netherlands / United States / / Currency pence / / Facility College Park / DSP Station / University of Maryland / University of California / / IndustryTerm post-processing step / loose interdependence algorithm / real-time implementations / minimum positive integer solution / non-uniform filter bank structures / explicit software control / uniprocessor scheduling algorithms / loose interdependence algorithms / acyclic scheduling algorithm / dynamic programming algorithm / heuristic solution / compiler technology / component sub-algorithms / tight scheduling algorithm / unambiguous protocol / improved integrated circuit technology / block diagram design tools / subindependence partitioning algorithm / programmable digital signal processors / programmable data signal processor / software implementation / digital signal processing applications / post-processing algorithm / aggressive imperative compiler technology / digital signal processing / / Organization Synchronous Dataflow Specifications SHUVRA S. BHATTACHARYYA Department / University of California / Berkeley / P2 / University of Maryland / College Park / P1 / Institute for Advanced Computer Studies / USA PRAVEEN K. MURTHY Angeles Design Systems EDWARD A. LEE Department of Electrical Engineering and Computer Sciences / / Person EDWARD A. LEE / PRAVEEN K. MURTHY / / Position hierarchical actor / actor / ith hierarchical actor / boundary actor / General / given actor / incident actor / same actor / digital audio tape player / high actor / compact disk player / source actor / sink actor / root actor / / ProgrammingLanguage C / C++ / / ProvinceOrState Maryland / British Columbia / California / / Technology three component algorithms / subindependence partitioning algorithm / tight scheduling algorithm / unambiguous protocol / uniprocessor scheduling algorithms / post-processing algorithm / 56000 programmable data signal processor / GDPPO algorithm / three component sub-algorithms / acyclic scheduling algorithm / two algorithms / compiler technology / programmable digital signal processors / RPMC algorithms / priority-based algorithm / improved integrated circuit technology / digital audio tape / DSP system / existing tight scheduling algorithm / dynamic programming algorithm / existing subindependence partitioning algorithm / DSP / Loose Interdependence Algorithms / loose interdependence algorithm / aggressive imperative compiler technology / / SocialTag 
Journal of VLSI Signal Processing 21, 151–[removed]c 1999 Kluwer Academic Publishers. Manufactured in The Netherlands. ° Synthesis of Embedded Software from Synchronous Dataflow Specifications SHUVRA S. BHATTACHARYY