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Cache / Central processing unit / CPU cache / Lookup table / Dynamic random-access memory / Cache algorithms / Computing / Computer memory / Computer hardware


Adaptive Mode Control: A Static-Power-Efficient Cache Design Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte Department of Electrical and Computer Engineering North Carolina State University {hzhou, mctobu
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Document Date: 2002-03-20 08:47:54

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File Size: 122,30 KB

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City

Austin / /

Company

Energy-Driven Integrated Hardware / Digital Equipment Corporation / Compaq / Power Aware Computer Systems / Ericsson / Intel / Low Power Electronics / VLSI Systems / /

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Facility

Computer Engineering North Carolina State University / hit/miss Data Store / North Carolina State University / University of Wisconsin-Madison / /

IndustryTerm

long-channel devices / adaptive algorithm / transistor-level energy model / control systems / banking / embedded processors / analytical energy models / update algorithm / negative feedback algorithm / energy efficient memory structure / deep sub-micron technologies / /

MarketIndex

IPC degradation for each / /

NaturalFeature

AutoBackgate-Controlled MT / /

Organization

Department of Electrical and Computer Engineering / National Science Foundation / AMC LIC / Thomas M. Conte Department of Electrical / Western Research Lab / University of Wisconsin / Computer Science Department / North Carolina State University / /

Person

Eric Rotenberg / Mark C. Toburen / Thomas M. Conte / /

Position

cache controller / /

Product

SimplePower / AutoBackgate-Controlled MT / /

ProvinceOrState

Wisconsin / /

PublishedMedium

Microprocessor Report / /

Technology

Memory Technology / GCR update algorithm / deep sub-micron technologies / jpeg / negative feedback algorithm / MIPS R10000 processor / perl / SRAM / simulation / adaptive algorithm / Integrated Circuit / /

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