| Document Date: 2014-08-13 13:31:19
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City Urbana / New Orleans / / Company IBM / Intel / dependencies LLC / / Currency AMD / USD / / / Facility University of Illinois / / IndustryTerm higher level software / software-controlled reconfigurable streaming / scientific applications / energy constraints / recent processors / software-controlled reconfiguration / similar processors / less energy savings / much hardware / software-controlled reconfigurable streaming buffer configuration / processor chips / high energy consumption / e.g. search queries / software-controlled reconfigurable streaming scheme / parallel clustering algorithm / crosslayer solution / energy sources / software overheads / per-processor / leakage energy / parallel management / energy savings / processor chip / commodity processors / energy reduction possibilities / energy / commodity chips / eDRAM technology / uncommon applications / cache energy savings / energy consumption / energy cost / power management / issue out-of-order processor / energy standpoint / extreme-scale computing / parallel services / structured grid applications / runtime systems / energy efficient decision / cache energy / speculative processor / cache energy saving / energy efficiency / streamer hardware / particle applications / energy consumption sources / cache energy consumption / power/energy efficiency / / MarketIndex FFT / / OperatingSystem L3 / / Organization Argonne National Lab / University of Illinois / Department of Computer Science / SESC / / Position cache controller / WB / representative / programmer / / Product Mantevo suite / Mantevo mini-app suite / Mantevo / / ProgrammingLanguage C / / ProvinceOrState Maryland / Illinois / Manitoba / / RadioStation Core / 8 Core / / Technology semiconductor / four processors / commodity processors / eDRAM technology / recent processors / processor chip / SRAM technology / parallel clustering algorithm / CMP / one processor / 4 issue out-of-order processor / load balancing / Interlagos processors / commodity chips / simulation / processor chips / /
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Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA E