Date: 2011-04-01 11:24:25Central processing unit Microprocessors Application checkpointing Computer memory Parallel computing CPU cache Multi-core processor AMD 10h Microarchitecture Computer architecture Computer hardware Computing | | Rebound: Scalable Checkpointing for Coherent Shared Memory Rishi Agarwal, Pranav Garg, and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,garg11,torrella}@illinois.eduAdd to Reading ListSource URL: iacoma.cs.uiuc.eduDownload Document from Source Website File Size: 286,85 KBShare Document on Facebook
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