![Central processing unit / Branch predictor / Instruction set architectures / Alpha 21264 / Register renaming / DEC Alpha / CPU cache / Out-of-order execution / Re-order buffer / Computer architecture / Computer hardware / Computer engineering Central processing unit / Branch predictor / Instruction set architectures / Alpha 21264 / Register renaming / DEC Alpha / CPU cache / Out-of-order execution / Re-order buffer / Computer architecture / Computer hardware / Computer engineering](https://www.pdfsearch.io/img/c89d99499e40a1ddace1b8573ed504d2.jpg)
| Document Date: 2003-06-11 14:31:51 Open Document File Size: 157,51 KBShare Result on Facebook
Company IBM / Motorola / Intel / Amdahl / / Event Product Issues / / Facility pipeline CS252/Culler Lec / Store Queue / / IndustryTerm transaction processing / n-issue processor / parallel algorithms / transistors/chip / / MarketIndex IPC 100 / IPC 35 / IPC 30 / / Organization ID IF IF / ID IF / / Person David E. Culler / Jim Smith / Dan Sorin / Max Max Max Max / / Position programmer / / Product Law / instruction / / ProgrammingLanguage FP / C / Fortran / / PublishedMedium Microprocessor Report / / Technology Alpha / n-issue processor / mpeg / Shared Memory / explicitly parallel algorithms / / URL www.MPRonline.com / /
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