IBM / MT RT RT RT / OPN / RT RT RT ET / Computer Sciences / /
Currency
USD / / /
Facility
Last store / External Store / store IDs / Store Queue ESN Miss Handler DSN OCN / Store ID EXIT / Computer Engineering The University of Texas / /
IndustryTerm
external store network / nearest-neighbor networks / on-chip network / operand network / large processors / given bank / contention accounting / cache bank / streaming applications / control processor / conventional processor / control networks / wide-issue processors / memory disambiguation hardware / on-chip data networks / processor control networks / metal / mesh router / operand router / ultra-low-latency micronetwork routers / signal processing library / 8KB cache bank / control network / optimization algorithms / control protocols / bank / 64KB bank / software model / mesh network / inter-processor / microarchitectural protocols / distributed banks / 16KB bank / dispatch network / hardware protocols / distributed microarchitectural protocols / data status network / bypass network / microarchitectural networks / status network / prototype chip / /
NaturalFeature
MT MT ET MT OCN MT MT MT MT MT MT PROC / MT ET ET ET ET ET ET ET ET PROC / /
Organization
University of Texas at Austin / ASIC / TRIPS Prototype Processor Karthikeyan Sankaralingam Ramadass Nagarajan Robert McDonald Rajagopalan DesikanÝ Saurabh Drolia M.S. Govindan Paul GratzÝ Divya Gulati Heather HansonÝ Changkyu Kim Haiming Liu Nitya Ranganathan Premkishore Shivakumar Simha Sethumadhavan Sadia SharifÝ Stephen W. Keckler Doug Burger Department of Computer Sciences ÝDepartment of Electrical / /
Person
Register Tile / Paul GratzÝ / Kim Haiming Liu Nitya Ranganathan / Heather HansonÝ / Stephen W. Keckler Doug Burger / /
Position
GT RT IT DT ET MT NT SDC DMA EBC C2C Chip / external bus controller / Prime Minister / callo RT / RT / ÙØ ÓÒ An RT / General / producer / controller / programmer / /