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City Barcelona / / Company IBM / Intel / / / Facility University of Rochester / Faster pipeline / Store Queue L1 D−Cache Int ALUs / Rochester Institute of Technology / Store ROB / / IndustryTerm control algorithms / synchronous processor / larger hardware / partial product / baseline processor / integer processing core / real-time constraints / energy / queue control algorithm / transaction processing / complexity adaptive processor / control algorithm / benchmark applications / technology file / cache algorithm / on-line adaption / adaptation algorithm / memory intensive applications / individual applications / deterministic algorithm / energy efficiency / aggressive superscalar processor / cross-product / adaptive control algorithms / / Organization Rochester Institute of Technology / Rochester / National Science Foundation / University of Rochester / Rochester / Register Update Unit / Department of Electrical and Computer Engineering / Department of Computer Science / Department of Computer Engineering / / Person Michael L. Scott / Steven Dropsho / Greg Semeraro / David H. Albonesi / Michael Scott / Jordi Girona / / / Position cache controller / controller / / ProgrammingLanguage FP / / ProvinceOrState New York / / RadioStation Work 1 / 100 / With 32 / / Technology Alpha / aggressive superscalar processor / RAM / adaptation algorithm / complexity adaptive processor / jpeg / resizing control algorithm / Phase-Adaptive cache algorithm / queue control algorithm / control algorithm / globally synchronous processor / adpcm / control algorithms / XScale processor / adaptive control algorithms / GSM / Phase-Adaptive processors / simulation / baseline processor / / SocialTag 
Improving Application Performance by Dynamically Trading Frequency for Complexity in a GALS Microprocessor∗ Greg Semeraro, David H. Albonesi, Steven Dropsho, Grigorios Magklis, and Michael L. Scott URCS Technical Repor