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Computing / CPU cache / Data dependency / Branch misprediction / Branch predictor / Instruction set / Memory disambiguation / Computer hardware / Central processing unit / Computer engineering


ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing ∗ Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou University of Illinois at Urbana-Champaign {sarangi,liuw
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Document Date: 2005-09-06 12:30:36

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File Size: 259,54 KB

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Company

AMD / IBM / Intel / /

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Facility

Yuanyuan Zhou University of Illinois / Inhibiting Store / A store / /

IndustryTerm

Software-based slicing / energy consumption / coherence protocol / energy / superscalar processors / /

Organization

TLS CMP / University of Illinois / National Science Foundation / /

Person

Entries Width (Bits) / Cache Size / Slice / Forward Slicing / Wei Liu / /

Position

RT / Forward / /

Product

ReSlice / /

ProgrammingLanguage

FP / C / C++ / /

ProvinceOrState

South Dakota / /

Technology

coherence protocol / shared memory / CMP / /

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