![Signal integrity / Design closure / Static timing analysis / Timing closure / Delay calculation / Application-specific integrated circuit / Design flow / Clock distribution network / Parasitic extraction / Electronic engineering / Electronic design automation / Signoff Signal integrity / Design closure / Static timing analysis / Timing closure / Delay calculation / Application-specific integrated circuit / Design flow / Clock distribution network / Parasitic extraction / Electronic engineering / Electronic design automation / Signoff](https://www.pdfsearch.io/img/2ba0cd127237d44102724f0bf6acb34d.jpg)
| Document Date: 2015-02-18 15:15:31 Open Document File Size: 406,89 KBShare Result on Facebook
Company RTL / Synopsys Inc. / PrimeTime PrimeTime / / Country United States / / Event Force Majeure / / IndustryTerm nextgeneration on-chip variation solution / industry goldstandard solution / cross voltage domain paths technology / threaded parallel processing / semiconductor design tools / point tools / instance chips / signoff tool / static timing analysis tools / hierarchical analysis technology / static timing analysis solution / signoff solutions / waveform propagation technology / statistical technology / powersensitive applications / static timing solution / standalone solutions / multicore computing / signoff solution / / OperatingSystem SUSE / Linux / ECOs / / Organization ASIC / COT / / Position driver / designer / / Product PrimeTime ADV / PrimeTime SI / PrimeTime / PrimeTime PX / Synopsys PrimeTime / / ProgrammingLanguage RC / / Technology semiconductor / ASIC / Linux / Hierarchical Timing Analysis technology / HyperScale hierarchical analysis technology / ultra-low voltage FinFET technology / waveform propagation technology / caching / cross voltage domain paths technology / simulation / instance chips / parallel processing / GUI / / URL www.synopsys.com / http /
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