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Computer memory / Central processing unit / Branch predictor / Hazard / CPU cache / Dynamic random-access memory / Dynamic voltage scaling / Microarchitecture / Design closure / Computer hardware / Electronic engineering / Computer architecture
Date: 2011-12-14 11:29:00
Computer memory
Central processing unit
Branch predictor
Hazard
CPU cache
Dynamic random-access memory
Dynamic voltage scaling
Microarchitecture
Design closure
Computer hardware
Electronic engineering
Computer architecture

Identifying and Predicting Timing-Critical Instructions to Boost Timing Speculation Jing Xin and Russ Joseph Department of EECS Northwestern University

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