<--- Back to Details
First PageDocument Content
Computational complexity theory / Logic gates / Circuit complexity / Secure multi-party computation / Levenshtein distance / XOR gate / Boolean circuit / Circuit / Adder / Theoretical computer science / Applied mathematics / Cryptographic protocols
Date: 2011-06-09 13:31:32
Computational complexity theory
Logic gates
Circuit complexity
Secure multi-party computation
Levenshtein distance
XOR gate
Boolean circuit
Circuit
Adder
Theoretical computer science
Applied mathematics
Cryptographic protocols

Faster Secure Two-Party Computation Using Garbled Circuits Yan Huang David Evans University of Virginia

Add to Reading List

Source URL: www.usenix.org

Download Document from Source Website

File Size: 414,79 KB

Share Document on Facebook

Similar Documents

On teaching fast adder designs: revisiting Ladner & Fischer∗ Guy Even †  February 1, 2006

On teaching fast adder designs: revisiting Ladner & Fischer∗ Guy Even † February 1, 2006

DocID: 1t36x - View Document

adder.c  1/1 lectures/1/src/ 1:

adder.c 1/1 lectures/1/src/ 1:

DocID: 1t0Io - View Document

CLASS RULESNT SHOOTOUT All run 1/8th mile. Heads Up no times displayed. Any power adder.

CLASS RULESNT SHOOTOUT All run 1/8th mile. Heads Up no times displayed. Any power adder.

DocID: 1sxkU - View Document

cs281: Introduction to Computer Systems  Lab03 – K-Map Simplification for an LED-based Circuit Overview In this lab, we will build a more complex combinational circuit than the mux or sum bit of a full adder that

cs281: Introduction to Computer Systems Lab03 – K-Map Simplification for an LED-based Circuit Overview In this lab, we will build a more complex combinational circuit than the mux or sum bit of a full adder that

DocID: 1srjK - View Document

VII Latin American Symposium on Circuits and Systems (LASCASArea-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design Azadeh Alsadat Emrani Zarandi1, Amir Sabbagh Molahosseini2, Leonel Sousa3

VII Latin American Symposium on Circuits and Systems (LASCASArea-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design Azadeh Alsadat Emrani Zarandi1, Amir Sabbagh Molahosseini2, Leonel Sousa3

DocID: 1sa34 - View Document