Optimizing S-box Implementations for Several Criteria using SAT Solvers Ko Stoffelen Radboud University, Digital Security, Nijmegen, The Netherlands

First Page		Document Content
Date: 2018-02-09 07:40:06 Logic gates Theoretical computer science Boolean satisfiability problem XOR gate XNOR gate AND gate Data Encryption Standard OR gate Block cipher Mathematical optimization Circuit		Optimizing S-box Implementations for Several Criteria using SAT Solvers Ko Stoffelen Radboud University, Digital Security, Nijmegen, The Netherlands Add to Reading List Source URL: ko.stoffelen.nl Download Document from Source Website File Size: 365,04 KB Share Document on Facebook

	CS61c: Representations of Combinational Logic Circuits J. Wawrzynek October 12, 2007 1 DocID: 1r4rE - View Document
	cs281: Introduction to Computer Systems Project Lab 2, Part I: Logisim and an Arithmetic Logic Unit (ALU) Library Assigned: Friday, Sept. 25, Due: Wednesday Sept. 30 by midnight 1. The purpose of this project laborator DocID: 1qUzK - View Document
	Proceedings of the International MultiConference of Engineers and Computer Scientists 2012 Vol II, IMECS 2012, March, 2012, Hong Kong A Concurrent Error Detection Based FaultTolerant 32 nm XOR-XNOR Circuit Implem DocID: 1pzE3 - View Document
	CS61c: Combinational Logic Blocks J. Wawrzynek October 12, 2007 1 DocID: 1oMax - View Document
	Faster Secure Two-Party Computation Using Garbled Circuits Yan Huang David Evans University of Virginia DocID: 18e5k - View Document