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Computer programming / Lock / Non-blocking algorithm / Parallel computing / Critical section / OpenMP / Test-and-set / Barrier / Linearizability / Concurrency control / Computing / Concurrent computing


SPECULATIVE SYNCHRONIZATION: PROGRAMMABILITY AND PERFORMANCE FOR PARALLEL CODES PROPER SYNCHRONIZATION IS VITAL TO ENSURING THAT PARALLEL APPLICATIONS EXECUTE CORRECTLY. A COMMON PRACTICE IS TO PLACE
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Document Date: 2004-04-08 09:33:42

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City

Carlisle / A. Rogers / /

Company

ACM Press / IEEE CS Press / /

Currency

USD / /

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Event

Product Recall / Product Issues / /

Facility

Cornell University / Frank H.T. Rhodes Hall / Stanford University / University of Illinois / José F. Martínez Cornell University Josep Torrellas University of Illinois / /

IndustryTerm

parallel applications / manner using hardware / coherence protocol / cache controller services / cache coherence protocol / speculative synchronization hardware / hardware-software interaction / /

Organization

University of Illinois / ACM / Technical Committee on Computer Architecture / National Science Foundation / Stanford University / Spanish government / IEEE Computer Society / Cornell University / /

Person

José F. Martínez / Josep Torrellas / Morgan Kaufmann / /

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Position

cache controller / vice-chair / assistant professor / professor of computer science / producer / controller / programmer / assistant professor of electrical and computer engineering / member / /

Product

M-16 / R1 / /

ProgrammingLanguage

C / /

ProvinceOrState

Illinois / /

SportsLeague

Stanford University / /

Technology

16 processors / API / coherence protocol / underlying cache coherence protocol / Caching / 64 processors / operating system / Operating Systems / local processor / /

URL

http /

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