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Central processing unit / Computer memory / Register renaming / Register file / CPU cache / Branch predictor / Parity bit / 64-bit / Processor register / Computer hardware / Computer architecture / Computing


Using Register Lifetime Predictions to Protect Register Files Against Soft Errors∗ Pablo Montesinos, Wei Liu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {pmontesi, liuw
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Document Date: 2007-04-07 18:15:20


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File Size: 614,05 KB

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Computer Science University of Illinois / /

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out-of-order superscalar processor / outof-order processor / replacement algorithm / electronics / computing / out-of-order processors / high-energy particles / energy / /

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SDC AVF / University of Illinois / DUE AVF / National Science Foundation / DED / Josep Torrellas Department / SESC / U.S. Securities and Exchange Commission / /

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Wei Liu / /

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datum / /

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New Jersey / /

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out-of-order superscalar processor / out-of-order processors / Shield replacement algorithm / simulation / outof-order processor / /

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