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City Princeton / Cambridge / / Company ABC / Actel Corp. / Synopsys / Computation Laboratory / Harvard University Press / Altera Corp. / Intel / Xilinx / / / Facility S. Plaza / Computation Laboratory of Harvard University / University of Michigan / University of California / / IndustryTerm technology mappers / combinational network / minimum solution / good-quality technology / smallest network / given network / i.e. networks / particular technology / Technology mapping / multi-valued functional decomposition algorithms / default technology / depth-optimal area optimization mapping algorithm / technology mapping algorithm / search space / mapped network / decomposition algorithm / / MusicGroup ABC / / Organization Harvard University / University of Michigan / University of California / Berkeley / LUT Structures Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS / / Person Robert Brayton / Y. Hu / V / Stephen Jang / Van Nostrand / / Position hb / representative / / ProvinceOrState New Jersey / Michigan / / Technology Boolean decomposition algorithm / FPGA / RAM / proposed Boolean matching algorithm / heterogeneous FPGA technology / good-quality technology / particular technology / proposed algorithms / 5.2 Algorithm / retiming-based technology mapping algorithm / multi-valued functional decomposition algorithms / default technology / pdf / FPGA technology / LUT-based FPGA technology / Technology mapping Technology / DSD / proposed algorithm / area optimization mapping algorithm / Boolean matching algorithm / flash / / URL http / SocialTag 
Fast Boolean Matching for LUT Structures Alan Mishchenko Satrajit Chatterjee Robert Brayton