| Document Date: 2006-08-09 21:17:41
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City San Jose / / Company ABC / Altera / Actel Corporation / AIG / Intel / / Currency USD / / / Event Reorganization / / IndustryTerm elegant algorithm / technology mapping / logic synthesis algorithms / conventional algorithm / depth optimal technology / macrocell mapping algorithm / re-writing algorithm / technology mapping algorithm / synthesis algorithms / / Organization Cuts Satrajit Chatterjee Alan Mishchenko Robert Brayton Department / UC Berkeley / MARCO Focus Center for Circuit and System Solution / / Person Alan Mishchenko Robert Brayton / / Position representative / Forward / / Product ProASIC3 / / ProgrammingLanguage ABC / / Technology FPGA / good depth using Algorithm / RAM / synthesis algorithms / elegant algorithm / macrocell mapping algorithm / 6.2 Mapping Algorithm / re-writing algorithm / logic synthesis algorithms / technology mapping algorithm / 5.1 Conventional Algorithm / Flash / conventional algorithm / CAD / / URL http /
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Factor Cuts Satrajit Chatterjee Alan Mishchenko Robert Brayton Department of EECS U. C. Berkeley {satrajit, alanmi, brayton}@eecs.berkeley.edu