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Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton
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Document Date: 2006-10-04 01:10:16


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Company

IBM / ABC / Lehman / /

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Facility

University of California / /

IndustryTerm

cut enumeration algorithm / structural technology / technology-independent synthesis algorithms / intermediate networks / technology mapping / Equivalent networks / intermediate network / conventional algorithm / terms network / combinational network / final network / Recent advanced algorithms / /

Organization

University of California / Berkeley / LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS / /

Person

Alan Mishchenko Satrajit Chatterjee Robert / /

Position

representative of the best structural technology / class representative / /

ProvinceOrState

Oregon / /

TVShow

Q.E.D. 4 / /

Technology

FPGA / cut enumeration algorithm / computation Structural technology / RAM / synthesis algorithms / proposed algorithm / simulation / Integrated Circuits / FPGA technology / conventional algorithm / LUT-based FPGA technology / CAD / /

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