| Document Date: 2008-04-03 12:04:29
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Company Synopsys / ABC / Altera / Xilinx / Intel / Actel / / Facility Minaret Runtime / Robert K. Brayton University of California / / IndustryTerm logic network / min-register algorithms / infeasible retiming solutions / logic networks / feasible solution / binary search / synthesis applications / intermediate solutions / improved timing feasible solution / register-minimizing retiming algorithm / verification applications / overall algorithm / acyclic combinational network / optimum solution / delay-minimizing retiming algorithms / foundational flow-based register minimization algorithm / intermediate solution / unconstrained register minimization algorithm / heuristic solutions / / MusicGroup ABC / / Organization Robert K. Brayton University / National Science Foundation / University of California / Berkeley / / Person D.R. Singh / V / MIN-REGISTER RETIMING / MIN-REG RETIMING ALGORITHM / Aaron P. Hurst / Alan Mishchenko / MIN-REG RETIMING / / Position radar12 oc wb / perf oc pci oc wb / forward / General / / ProvinceOrState California / / TVStation TFO / / Technology FPGA / delay-minimizing retiming algorithms / Minaret algorithm / proposed algorithm / known retiming algorithms / B. Iterative Refinement The overall algorithm / retiming algorithm / unconstrained register minimization algorithm / 2 ALGORITHM / never 4 ALGORITHM / known timing-constrained min-register algorithms / register-minimizing retiming algorithm / foundational flow-based register minimization algorithm / Terms Algorithms / CAD / / URL http /
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1 Scalable Min-Register Retiming Under Timing and Initializability Constraints Aaron P. Hurst, Alan Mishchenko, and Robert K. Brayton University of California, Berkeley