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Electrical circuits / Electronic design / Synchronization / Asynchronous circuit / Asynchronous system / Digital electronics / Logic synthesis / CPU design / VHDL / Electronic engineering / Electronic design automation / Central processing unit


FINAL REPORT (GR/S12036) Synthesis and Testing of Low-Latency Asynchronous Circuits (STELLA) A.Yakovlev, A. Bystrov, A.M.Koelmans, G. Russell and D.J.Kinniment (School of Electrical, Electronic and Computer Engineering,
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Document Date: 2006-06-07 13:42:56

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File Size: 73,31 KB

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City

St. Rafael / Stara Lesna / Birmingham / Oxford / Manchester / Turku / New Orleans / Munich / Como / Vancouver / Scottsdale / Cambridge / Beijing / Miami / Edinburgh / /

Company

AES / Atmel / NEC / Sun Microsystems / Southampton University / MBDA UK Ltd / IEEE CS Press / IEEE Comp / CSC / Atmel Smart Cards UK / FTL Systems / Asynchronous Systems Laboratory / Handshake Solutions / Silistix / Intel / /

Country

Italy / France / Slovakia / United Kingdom / China / Finland / /

Event

Business Partnership / FDA Phase / /

Facility

University of Newcastle / Asynchronous Systems Laboratory / Newcastle University / St Anne's College / Institute of Electronics / Xidian University / Duplex Communication System / /

IndustryTerm

test algorithms / software error / performance analysis tool / software tools / e-book / online testing / conference travel / error handling infrastructure / on developing software tools / synthesis tools / demonstrator chip / non-invasive online checkers / on-line testing / self-timed on-chip communications / systems / industrial applications / on-line checkers / on-line testing research / concurrent systems / interconnection technology / on-line and off-line testing / dependable hardware / on-line monitors / Online Testing Symposium / /

Organization

Chinese Academy of Sciences / School of Electrical / Electronic and Computer Engineering / Newcastle University / UC Berkeley / Merz Court / University of Newcastle / Xidian University / EPSRC / Univ. of Newcastle / Institute of Electronics / School of EECE / St Anne's College / European Union / IEEE Computer Society / /

Person

A.Bystrov / P. Wang / F. Xia / D. Shang / D. Sokolov / C. D'Alessandro / S. Dasgupta / J.P. Murphy / D. Koppad / F. Burns / A. Madalinski / J. Murphy / A. Yakovlev / P. Hyde / /

Position

J Marshall / D. J. / Prime Minister / D.J. / low latency controller / controller / /

Product

Low Latency Asynchronous / /

ProgrammingLanguage

Verilog / /

ProvinceOrState

Arizona / /

PublishedMedium

IEEE Transactions on Computers / /

Technology

datapath protocols / self-checking RISC-based processor / 4-phase protocols / interconnection technology / VHDL / same chip / test algorithms / Verilog / demonstrator chip / self-checking RISC processors / CAD / /

URL

http /

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