Back to Results
First PageMeta Content
Central processing unit / Parallel computing / Chunk / Process / CPU cache / Computer architecture / Computing / Computer hardware / Computer memory


do i:[removed][removed] Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas
Add to Reading List

Document Date: 2010-12-26 23:39:42


Open Document

File Size: 974,20 KB

Share Result on Facebook

City

Proc P0 P2 / Two Hardware / New York / Diego / San Diego / /

Company

Sun Microsystems / Computer Sciences / Rerun Hardware / RERUN Wisconsin / L2 Bank / Intel / Microsoft / /

Country

United States / /

Currency

pence / AMD / USD / /

/

Event

M&A / /

Facility

Pipeline References / Computer Science Department University of Illinois / Engineering University of Washington / Computer Sciences Department University of Wisconsin-Madison / O port / Computer Science Department University of Illinois Urbana-Champaign / /

IndustryTerm

tiny per-processor / hardware systems / system simulation infrastructure / time-travel debugger / cache bank / generic network / real time / commodity systems / correct software / per-processor / cache-coherent multicore chip / multicore systems / proposed hardware / multicore hardware / computer systems / replay systems / clock algorithm / bank / multiprocessor hardware / 5GHz processors / service providers using commodity hardware / hot-standby systems / /

Organization

University of Washington / National Science Foundation / University of Illinois / Department of Computer Science / US Federal Reserve / Computer Science Department University of Illinois Urbana-Champaign / SESC / University of Wisconsin / /

Person

Luis Ceze / Davis / Beckmann / Pablo Montesinos / Norman Jouppi / Mark D. Hill / Josep Torrellas Abstract Many / Derek R. Hower / Sorin / David Patterson / /

Position

Directory MTS Coherence controller / D.J. / log Interrupt I/O log log Arbiter / Harper / arbiter / tax advisor / Coherence controller / ID Arbiter / /

Product

Lamport / PicoLog / DeLorean / Wisconsin GEMS10 / /

ProvinceOrState

Wisconsin / Illinois / California / /

Technology

virtual machine / Lamport clock algorithm / cache-coherent multicore chip / log Interrupt I/O log log Arbiter Processor / eight 5GHz processors / relevant processors / shared memory / Operating Systems / committing processor / arbiter.3 The processor / paging / tiny per-processor / simulation / Sequential consistency / /

URL

http /

SocialTag