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City Austin / Barbara Santa Barbara / / Company Altera / Toshiba / Trustworthy Systems / AMD / Intel / the AES / / Currency USD / / / Event Reorganization / FDA Phase / / Facility Store Instruction / Computer Science University of California / / IndustryTerm proposed hardware solution / offchip co-processor / security applications / interconnect technologies / hardware solutions / advantages to competing chip / simultaneous multithreading processor / multi-core processors / 45nm predictive technology models / software implementations / greater thermal management / real time / security device / less costly product / different metal layers / co-processor solution / manufacturing custom hardware / commodity systems / cache eviction protocol / cryptographic algorithm / multi-core processor / cache protocol / metal layers / offchip / commodity chip / chip co-processor / commodity processors / commodity computing hardware / metal / components on-chip / potential applications / marketed technology / cache management / low volume products / Concurrent processing platforms / sample commodity processor / cryptographic hardware / shared bus protocol / resources on-chip / functional systems / commodity processor / assurance systems / expected manufacturing yield / software solutions / high assurance processing / on-chip / co-processor / bus protocols / / MarketIndex CPU / SPEC / / Organization University of California / Hardware Trust / Naval Postgraduate School / Crypto Control Unit / Computer Science and Engineering Univ. of California / Department of Electrical and Computer Engineering / Secure Alternate Service / / Person Grant Secure / Timothy Sherwood / Max Frequency / Jonathan Valamehr / Grant Memory / Mohit Tiwari / Ryan Kastner / Cynthia Irvine / Timothy Levin / Ted Huffmire / / / Position Cache Controller / cache and cache controller / trusted arbiter / spy / cache/cache controller / underlying cache/cache controller / Controller / / Product PTLsim / Disabling / Spice / SPEC2000 / this / / ProgrammingLanguage Verilog / / ProvinceOrState California / / Technology cache eviction protocol / 3-D / underlying chip / sample commodity processor / 3-D chips / shared bus protocol / 3-D Control Plane To Processor / commodity processors / commodity chip / cache memory / mobile phones / operating system / components on-chip / shared memory / integrated circuits / simultaneous multithreading processor / cryptographic algorithm / encryption / cryptography / chip co-processor / main processor / Verilog / 3-D interconnect technologies / existing technology / 3-D technology / commodity processor / 3-D system / bus protocols / Simulation / TDMA / resources on-chip / cache protocol / offchip co-processor / already marketed technology / integrated circuit / attacked using the cache eviction protocol / / SocialTag 
Hardware Assistance for Trustworthy Systems through 3-D Integration Jonathan Valamehr† , Mohit Tiwari‡ , and Timothy Sherwood‡ † Department of Electrical and Computer Engineering