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Company IBM / / / Facility By building / terminal P / University of California / / IndustryTerm on-chip processors / interconnect network / reconfigurable devices / reconfigurable hardware / even entire customized processors / allowed communications / parallel search / reconfigurable systems-on-chip / sub-systems / field programmable devices / software designers / generalpurpose processors / few embedded processors / purpose processor / streaming applications / faster processing / fewer reconfigurable devices / reconfigurable device / memory management / scheduled routing hardware / reconfigurable systems / / Organization University of California / ASIC / Naval Postgraduate School Department of Computer Science Monterey / Santa Barbara Department of Computer Science Santa Barbara / University of California / San Diego Department of Computer Science and Engineering La Jolla / / Person Ryan Kastner / Timothy Sherwood / Timothy Levin / / / Position security guard / M2 M1 M2 Arbiter Arbiter Arbiter Arbiter / engineer / / ProgrammingLanguage Verilog / Yacc / / Technology encryption / few embedded processors / FPGA / FPGA chip / generalpurpose processors / RAM / ASIC / reconfigurable systems-on-chip / Verilog / 200 separate RISC processors / on-chip processors / SDRAM / purpose processor / SRAM / operating system / virtual memory / shared memory / Flash / / SocialTag 
Enforcing Memory Policy Specifications in Reconfigurable Hardware Ted Huffmire , Timothy Sherwood† , Ryan Kastner‡ , and Timothy Levin Naval Postgraduate School