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Computer architecture / Computer memory / Microprocessors / Threads / CPU cache / Cache / Memory hierarchy / Microarchitecture / Parallel computing / Computer hardware / Computing / Central processing unit


RE SE A RCH F E AT U RE Concurrent Average Memory Access Time Xian-He Sun and Dawei Wang,
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Document Date: 2014-05-30 12:12:22

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IBM / Argonne National Laboratory / Scalable Computing Software Laboratory / The MCD / Intel / Juniper Networks / Advanced Micro Devices / Modeling Networked Systems / /

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Institute of Computing Technology / Scalable Computing Software Laboratory / #cache port / Illinois Institute / Illinois Institute of Technology / Michigan State University / /

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L3 / /

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Michigan State University / ASIC / Chinese Academy of Sciences / National Science Foundation / Illinois Institute of Technology Traditional / Department of Computer Science / Illinois Institute of Technology / Institute of Computing Technology / IEEE Computer Society / /

Person

Xian-He Sun / Morgan Kaufmann / /

Position

professor of computer science and chair / distinguished professor / postdoctoral researcher / design engineer / http /

Product

Nehalem CPU / /

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Core / /

Technology

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