Parallel Computing–248 www.elsevier.com/locate/parco A compiler tool to predict memory hierarchy performance of scientific codes q B.B. Fraguela a, R. Doallo

Source URL: www.des.udc.es

• Cache
• Compiler optimizations
• Computer memory
• Computer architecture
• Software optimization
• CPU cache
• Optimizing compiler
• Locality of reference
• Automatic parallelization
• Infinite loop
• Memory hierarchy
• Lookup table

Design of Parallel and High-Performance Computing Fall 2014 Lecture: Cache Coherence & Memory Models Instructor: Torsten Hoefler & Markus Püschel

Source URL: spcl.inf.ethz.ch

• Computer architecture
• Computer memory
• Cache coherency
• Concurrent computing
• Parallel computing
• Cache
• Random-access memory
• Shared memory
• CPU cache
• Memory hierarchy

Case study with atop: memory leakage Gerlof Langeveld & Jan Christiaan van Winkel www.atoptool.nl – May 2010 – This document describes the analysis of a slow system suffering from a process with a memory leakage. Suc

Source URL: www.atoptool.nl

• Memory management
• Virtual memory
• Paging
• Page cache
• Slab allocation
• C dynamic memory allocation
• Page
• Virtual address space
• Memory leak
• Cache
• Page table
• Zswap

Faster Fourier Transforms via Automatic Program Specialization Julia L. Lawall IRISA { Compose group Campus Universitaire de BeaulieuRennes Cedex, France

Source URL: repository.readscheme.org

• Digital signal processing
• Cache
• Computer memory
• Compiler optimizations
• Algorithms
• Divide and conquer algorithms
• Fast Fourier transform
• CPU cache
• Optimizing compiler
• Partial evaluation
• Speedup
• Template

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Source URL: www.visitdevon.co.uk

GC-IRL API Specification VersionThe GC-IRL The Global Caché GC-IRL IR Learner plugs into the RS232 port of any PC and is used to learn the full spectrum, 30KHz to 500KHz, of IR codes that control infrared driven

Source URL: www.globalcache.com

• Remote control
• Assistive technology
• Humanmachine interaction
• RS-232
• Serial port
• Infrared

Performance Portable Optimizations for Loops Containing Communication Operations Costin Iancu Wei Chen, Katherine Yelick

Source URL: crd.lbl.gov

• Compiler optimizations
• Loop optimization
• Automatic parallelization
• Loop nest optimization
• CPU cache
• Program optimization
• Software pipelining
• Lookup table
• Distributed computing
• Fortran
• Compiler
• Algorithm

Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc

Source URL: crd.lbl.gov

• Computer memory
• Cache
• Computer architecture
• Compiler optimizations
• CPU cache
• Central processing unit
• Opteron
• Cell
• Sparse matrix-vector multiplication
• Loop nest optimization
• Multi-core processor
• Advanced Micro Devices

RDMA with PMEM Software mechanisms for enabling access to remote persistent memory Chet Douglas Intel Corporation

Source URL: www.snia.org

• Computer memory
• Remote direct memory access
• Persistent memory
• CPU cache
• Cache
• ISCSI Extensions for RDMA

L OW E R M I S S I S S I P P I V A L L E Y J O I N T V E N T U R E MBCC Approves Nearly $7MM for Conservation within the LMVJV The Lower Mississippi Valley Joint Venture is a

Source URL: www.lmvjv.org

• Aquatic ecology
• Cache River National Wildlife Refuge
• Ducks Unlimited
• Palustrine wetland
• Cache River
• Wetland
• Catahoula National Wildlife Refuge