Back to Results
First PageMeta Content
Cache coherency / Parallel computing / Computer memory / Microprocessors / Central processing unit / CPU cache / Multi-core processor / MESI protocol / Cache coherence / Computing / Computer hardware / Computer architecture


´ Ecole Polytechnique F´ ed´ erale de Lausanne, Switzerland
Add to Reading List

Document Date: 2010-01-19 05:45:28

Open Document

File Size: 767,70 KB

Share Result on Facebook

City

Lausanne / /

Company

Multicore Systems / Multiprocessor Systems / /

Facility

Hybrid JETTY / Include JETTY / /

IndustryTerm

snoopy hardware coherence protocols / minimal energy configuration / parallel applications / energy consumption / purpose computing / embedded systems / magnetic core devices / snoop energy / purpose computing market / software applications / snoopy based cache coherence protocols / software level / less energy / software developers / manufacturing / high-tech device / computing / hardware cache coherency protocols / on-chip / chip manufacturing cost / memory subsystem energy / semiconductor chips / fabrication technologies / energy / /

MarketIndex

EEMBC / /

Organization

Ecole Polytechnique F´ ed´ / Memory Organisation of Multiprocessor Systems / ded / /

Person

Theo Kluter Philip Brisk Paolo / /

Position

MPSoC Embedded Systems Advisors / /

Technology

semiconductor / shared memory system / RAM / fabrication technologies / snoopy hardware coherence protocols / hardware cache coherency protocols / smart phones / semiconductor chips / 2.4 Cache Coherence Protocols / random access / Shared Memory / MESI Protocol / snoopy based cache coherence protocols / integrated circuits / /

SocialTag