| Document Date: 2006-09-12 12:06:57
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City Cairns / / Company Tiled CMP On-Chip Networks / Cadence Design Systems / Hx (34) NETWORKS / / Country Australia / / Currency USD / / / Facility William J. Dally Computer Systems Laboratory Stanford University / / IndustryTerm parallel network / technology models / representative technology / energy consumption increase / worst energy / torus network / analytic energy model / excess energy dissipation / on-chip interconnection networks / area-delay product / semi-global metal layers / metal tracks / empty network / energy-delay product / energy-delay measure / router services / downstream router / direct networks / Local metal / Channels connecting routers / area-delay and energy-delay metrics / semi-global metal / energy / on-chip networks / radix routers / metal / channel energy model / interconnection network / unused lower metal layers / metal layer / well designed network / energy consumption / energy dissipation / onchip networks / worse energy efficiency / inthe routers / technology model / tree networks / consistency protocols / energy efficiencies / area-efficient and energy-efficient on-chip networks / local metal layers / indirect network / energy efficiency / metal pitch / energy models / insight into interconnection network / mesh networks / predictive technology models / / Movie North and South / / Organization FTree TTree / TTree FTree / Stanford University / / Person Cid Cti Cto / Packet Latency / Cell Height (Hcell) / Cell Width (Wcell) / William J. Dally / / Position Cto / driver / Prime Minister / model an abstract communication / wordline driver / bitline driver / input driver / representative / / Product M-16 / / ProgrammingLanguage Mathematica / / ProvinceOrState Queensland / / SportsLeague Stanford University / / Technology 1 Processor Tile Processor / 4.1 Router / four processors / consistency protocols / 5-output router / representative technology / 1 1 2 1 Processor Tile Processor / 64 processors / 8-input / 8-output router / SRAM / 65nm CMOS technology / 4.2 protocol / downstream router / CMP / INTRODUCTION Chip / high radix routers / 2 2 3 3 3 3 1 3 2 Processor / 8 Router / VLSI technology / 2.3 Technology / load balancing / previous router / flow control / bypassed router / Channels connecting routers / inthe routers / VLSI technologies / simulation / O1TURN algorithm / 5 Router / routing algorithm / /
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Design Tradeoffs for Tiled CMP On-Chip Networks ∗ James Balfour , William J. Dally Computer Systems Laboratory Stanford University