| Document Date: 2012-07-05 23:25:37
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Company DRAM / Commodity Memory Systems / Google / LOT-ECC / A. / HP Labs / Intel / / Currency AMD / / / Event Reorganization / FDA Phase / / Facility University of Utah / Naveen Muralimanohar‡ Rajeev Balasubramonian† Al Davis† Norman P. Jouppi‡ University of Utah / / IndustryTerm close-page row-buffer management / largescale systems / interconnect technologies / energy consumption lies / erroneous chip / contemporary high-end server processors / chipkill-correct systems / 5500based systems / x4 chip / narrow chips / memory systems / chipkill solutions / energy / wider chip / energy consumption / energy-efficiency / x8 chips / hardware/software support mechanisms / chip / increased energy consumption / x16 chips / bank/rank/channel contention / 7500based systems / rank-level/bank-level parallelism / x8 chip / bank utilization / Bank contention / x4 devices / / Organization G8 / National Science Foundation / DIMM / rank / University of Utah / G7 / / Person Schroeder / Aniruddha N. Udipi / Norman P. Jouppi / Rajeev Balasubramonian† Al Davis / / Position memory controller / controller / / Product x8 / DDR3 / / ProgrammingLanguage C / / ProvinceOrState Utah / Pennsylvania / / RadioStation Work 2.1 / / Technology least 2 chips / same chips / also 18 x8 chips / 56 Chip / eighteen x8 chips / x16 chips / wider I/O chips / 5 chips / 9 chips / x8 chip / 18 chips / 7 Chip / nine chips / server processors / ninth chip / second chip / thirty-six x8 chips / operating system / failed chip / operating systems / same chip / one ECC chip / just nine x8 chips / 1 dead chip / 8 data chips / 8 Chip / DSD / 55 T4 T4 Chip / 1 chip / eight chips / 255 data chips / three ECC chips / nine x8 chips / JEDEC protocol / 7 PPA 1b T4 Chip / affected chip / eight data chips / fifteen data chips / x4 chip / caching / 9th chip / 0 Chip / 55 PPA PPB Chip / simulation / DDR3 protocol / eighth chip / dedicated ECC chip / 18 x8 chips / 2 chips / erroneous chip / /
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LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems ∗ Aniruddha N. Udipi† † Naveen Muralimanohar‡