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ECC memory / Error detection and correction / Interrupt / Hamming code / Information / Universal asynchronous receiver/transmitter / Chipkill / Unbuffered memory / Computer memory / Computer architecture / Computing


Error Checking and Correction (ECC) Controller
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Document Date: 2014-08-20 16:09:24


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File Size: 256,21 KB

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City

San Jose / /

Company

Send Feedback Changes Initial Release Altera Corporation / Altera Corporation / Correction Controller Send Feedback Altera Corporation / Error Checking / System Integration ECC / The ECC / /

Facility

Single port USB RAM / port NAND Write FIFO / port EMAC RX FIFO / port NAND Read FIFO / port DMA FIFO / Single port SD/MMC FIFO / stall Display / port NAND ECC Buffer / port EMAC TX FIFO / /

IndustryTerm

software configuration / changes to any products / semiconductor products / /

OperatingSystem

L3 / /

Organization

U.S. Patent and Trademark Office / /

Person

Each / Send Feedback / Block Diagram / /

Position

Reset Manager / ECC Controller Functional Description Overview The ECC controller / SD/MMC controller / RAM controller / The Reset Manager / Manager level / manager / generic / Clock Manager / Manager section / flash controller / ECC controller / Manager For / Manager Peripheral IP ECC Controller Initialization Block Memory Slave Interface IMAM From Interconnect ECC / The ECC controller / Testing The ECC controller / Single-Bit Error Occurrence The ECC controller / Manager chapter / Security Manager / System Manager / / Information Clock Manager / controller / Manager / fuses and software / Recent Error Address Registers The ECC controller / Correction Controller / /

ProvinceOrState

California / /

RadioStation

32 Word / 35 Word / 16 Word / /

Technology

semiconductor / Ethernet / RAM / ARM processor / flash / /

URL

www.altera.com/common/legal.html / www.altera.com / /

SocialTag