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POWER6 / Chipkill / CPU cache / IBM POWER / POWER5 / Dynamic random-access memory / Multi-core processor / RAM parity / IBM z10 / Computer memory / Computer hardware / Computing


HC19Fault – Tolerant Design of the IBM POWER6 Microprocessor.v6.ppt
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Document Date: 2013-07-27 23:58:01


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File Size: 1,35 MB

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City

Austin / /

Company

Checkpoint / IBM Corporation / /

Event

Product Issues / /

Facility

Main Store / /

IndustryTerm

2x4MB on-chip / frequency dual-core chip / alternate/spare processor / chip real estate / high energy radiation / /

OperatingSystem

UNIX / L3 / /

Organization

Decimal Floating Point Unit / Branch Unit Vector Multimedia Unit / /

Person

Spare Pins / Daniel Henderson / Scott Swaney / Pia N. Sanda / Jeffrey W. Kellington / /

Position

pin Memory Controller / controller / /

Product

location Firmware / cache / /

ProgrammingLanguage

D / /

RadioStation

Core 1 / Core / Core 2 / /

Technology

Alpha / 4 Hot Chips / radiation / errors Processor / 2x4MB on-chip / 18 Hot Chips / Floating Point Unit / 16 Hot Chips / 8 Hot Chips / 10 Hot Chips / Dataflow protection Protocol / 7 Hot Chips / alternate/spare processor Processor / 11 Hot Chips / lithography / 12 Hot Chips / 2 Hot Chips / SRAM / intermittent errors Alternate Processor / processor Instruction Retry Alternate Processor / UNIX Processor / 14 Hot Chips / /

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