| Document Date: 2009-05-14 10:14:09
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Company ClearSpeed AdvanceTM / Intel / / IndustryTerm considered software release / software design / technology offers / chosen algorithm / performance computing / time-consuming applications / high computing power / host processor / parallel data processing / software development kit / energy-efficient multicore processor design / application software / multi-threaded array processor / multicore technologies / purpose processor / dual-core processors / coprocessor technology / point applications / even solving matrix systems / system-on-a-chip / scientific computing / numerical solution / / Organization ClearSpeed AdvanceTM Accelerator Board / / Person Jan-Philipp Weiß / Vincent Heuveline / / Position programmer / / Product CSX600 / ClearSpeed CSX600 / / ProgrammingLanguage ANSI C / Mathematica / C / / ProvinceOrState Prince Edward Island / / Technology 3.2 Gbyte/s external bandwidth CSX600 processor / FPGA / coprocessor technology / multicore technologies / multi-threaded array processor / host processor / CSX600 processors / chosen algorithm / flow control / ANSI C / PCI-X / accelerator board / two CSX600 processors / ClearSpeed CSX600 chip / CSX600 processor / fluid dynamics / underlying algorithms / BGK lattice Boltzmann algorithm / system-on-a-chip / purpose processor / one CSX600 chip / simulation / operating system / 2 CSX600 processors / shared memory / integrated circuits / second CSX600 processor / currently existing technologies / /
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Technical Report A Parallel Implementation of a Lattice Boltzmann Method on the ClearSpeed AdvanceTM Accelerator Board Vincent Heuveline, Jan-Philipp Weiß