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Scalable Queue-Based Spin Locks with Timeout Michael L. Scott and William N. Scherer III Department of Computer Science University of Rochester Rochester, NY[removed] {scott,scherer}@cs.rochester.edu∗
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Document Date: 2001-05-18 16:44:10

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File Size: 198,10 KB

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Orlando / Scalable Queue / Snowbird / Cancun / /

Company

IBM / Computer Sciences / Compaq / Mercury Computer Corp. / /

Country

United States / Mexico / /

Currency

USD / /

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Facility

Computer Science University of Rochester Rochester / Swedish Institute of Computer Science / Building FIFO / University of Wisconsin / /

IndustryTerm

recent processors / spin lock algorithms / bank / active processors / synchronization algorithm / different processors / significant signal processing applications / fewer active processors / active processor / invalidation-based cachecoherence protocol / /

OperatingSystem

Sequent / /

Organization

Univ. of Washington / National Science Foundation / Computer Science University of Rochester Rochester / University of Wisconsin / Swedish Institute of Computer Science / /

Person

John Mellor / Michael L. Scott / Mark Hill / Vitaly Oratovsky / Socalled / William N. Scherer III / /

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Position

scheduler / head / /

ProgrammingLanguage

E / C / /

ProvinceOrState

Wisconsin / Utah / Florida / /

Technology

Alpha / Ethernet / two active processors / 16 processors / one active processor / 20 processors / 100 processor / Synchronization algorithms / one processor / TATAS algorithm / spin lock algorithms / Correctness Synchronization algorithms / 20 24 28 32 36 40 44 48 50 Processors / invalidation-based cachecoherence protocol / 250 MHz processors / different processors / same processor / 8 9 10 11 12 13 14 15 16 Processors / simulation / 40 44 48 50 4 8 12 16 20 Processors / html / 32 processors / fewer active processors / shared memory / synchronization algorithm / invoking processor / 44 processors / /

URL

www.cs.rochester.edu/u/scott/synchronization / /

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