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Conflict Exceptions: Simplifying Concurrent Language Semantics with Precise Hardware Exceptions for Data-Races Brandon Lucia† Luis Ceze†
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Document Date: 2010-04-14 00:55:30

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City

Saint-Malo / /

Company

Apache / Model Checking Concurrent Software / MySQL / HP Labs / Weak Memory Systems / 3M / Microsoft / CONCUR / /

Country

France / /

Currency

USD / /

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Event

FDA Phase / /

Facility

University of Washington / /

IndustryTerm

hardware/software / real large systems / vector clock algorithms / effect systems / mainstream applications / hardware transactional memory systems / multiprocessor systems / coherence protocol / cache coherence protocol / /

MarketIndex

PARSEC / OLTP / /

OperatingSystem

POSIX / /

Organization

University of Washington / National Science Foundation / SESC / /

Person

Joe Devietti / Dan Grossman / S. V. Adve / K. Gharachorloo / R. Bocchino / V / Tom Bergan / M. D. Hill / Stream Architectures (Multiprocessors) / Krste Asanovic / Luis Ceze† Karin Strauss / /

Position

cache controller / original writer / writer / Features General / programmer / /

Product

L1 / /

ProgrammingLanguage

Ada / Java / C / C++ / /

ProvinceOrState

South Carolina / Oregon / /

Technology

Object-Oriented Programming / vector clock algorithms / directory-based MOESI protocol / Java / coherence protocol / extended protocol / Simulation / sequential consistency / shared memory / cache coherence protocol / pdf / local processor / /

URL

http /

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