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Datasheet DC Ultra Concurrent Timing, Area, Power and Test Optimization Overview
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Document Date: 2015-03-19 18:15:41

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File Size: 558,94 KB

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Company

RTL / IBM / Synopsys Inc. / Sun Solaris (32-/64-bit) Synopsys Inc. / /

Country

United States / /

IndustryTerm

e-f / optimization technologies / topographical technology / place-and-route solution / datapath optimization algorithms / technology shares technology / synthesis solution / /

MusicAlbum

Area / Power / /

OperatingSystem

Sun Solaris / IBM AIX / Linux / /

Person

Cin Cin / /

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Position

sales representative / designer / /

ProgrammingLanguage

TCL / DC / Verilog / /

Technology

synthesis Area Reduction Technologies / synthesis use model DC Ultra Topographical technology / datapath optimization algorithms / Verilog / optimization technologies / synthesis solution Topographical Technology Topographical technology / Topographical technology shares technology / VHDL / Linux / /

URL

www.synopsys.com / http /

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