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Electronic design / Integrated circuits / Logic design / Semiconductor intellectual property core / XML / IP-XACT / Multi-core processor / Open Core Protocol / Application-specific integrated circuit / Electronic engineering / Computing / Electronics


1 An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing Nathaniel Rollins, Adam Arnesen, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC)
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Document Date: 2013-03-11 16:23:00

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File Size: 551,47 KB

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City

JHDL / /

Company

Xilinx Inc. / Sonics Inc. / /

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Facility

University of Tubingen / Port Grouping / /

IndustryTerm

carrier phase / design tools / software engineering / software productivity / compliant design tools / external tool / reconfigurable computing systems / level design tools / reconfigurable devices / party tool / reconfigurable computing development environment / compliant tools / reconfigurable computing / incompatible protocols / module generator tools / reconfigurable computing design environment / reconfigurable computing circuit / external tools / pre-defined bus protocols / low-level hardware / generation tools / communication protocol / design tool / computing / synthesis tools / generic design tool / level synthesis tool / lightweight communication protocols / software systems / reconfigurable systems / /

Organization

Brigham Young University / National Science Foundation / University of Tubingen / NSF Center for High-Performance Reconfigurable Computing / /

Person

Michael Wirthlin / James A. Rowson / Nathaniel Rollins / Roberto Passerone / Scott Hauck / Wolf-Dietrich Weber / Annette Reutter / Wolfgang Rosenstiel / Morgan Kauffman / Adam Arnesen / Andre DeHon / /

Position

hardware designer / designer / actual designer / /

ProgrammingLanguage

XML / Verilog / RC / XML Schema / /

Technology

FPGA / lightweight communication protocols / XML / Verilog / system-on-chip / communication protocol / Simulation / pre-defined bus protocols / VHDL / GUI / /

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