| Document Date: 2006-10-02 23:11:09
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City Phoenix / / Company IBM / Motorola / Programmable Hardware / AMD / RTL / Intel / / Currency pence / USD / / / Event Product Recall / Product Issues / / Facility Pipeline Post / Josep Torrellas University of Illinois / Pipeline Post Defects / EPIC arch / / IndustryTerm appropriate technology / clock distribution network / likely using string matching algorithms / on-chip hardware / recent processors / past and current processors / software patches / processor chips / translation software / software routines / verification tools / software workarounds / system software ones / software-intensive workarounds / multiprocessor systems / k-means clustering algorithm / to new processors / processor chip / software structure / multicore processors / system software writers / system software bugs / latter processor / formal verification tools / buggy hardware / thread-level speculation systems / train-set processors / recovery handler algorithm / running formal verification tools / / OperatingSystem L3 / / Organization National Science Foundation / Global Recovery Unit / SSU BDU / Signal Selection Unit / University of Illinois / Bug Detection Unit / Decode Unit / / Person Interrupt Handler Scheduler / Max Signal Latency / Subsystem Field Programmable Pass Transistor / Abhishek Tiwari / / Position power manager / dynamic power manager / manager subsystems / Mp / supervisor / Controller MP and Bus Unit Processor Status Manager / power control manager / Athl64 Mean L3 Tlb+Virtual Mp / Scheduler / manager module / memory controller / Controller / Producer / / Product Itanium 2 / / ProgrammingLanguage FP / / Technology design verification / same processors / appropriate technology / latter processor / 10 processors / Pentium processors / recovery handler algorithm / Phoenix Algorithm / 2 processors / train-set processors / Crusoe / processor chip / multicore processors / operating system / 3-step Phoenix algorithm / ten recent processors / 1 Label Processor / k-means clustering algorithm / paging / virtual memory system / five processors / virtual memory / likely using string matching algorithms / processor chips / unmodified processor / / URL http /
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Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware∗ Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas University of Illinois at Urbana-Champaign {sarangi,atiwari,tor