![](https://www.pdfsearch.io/img/d9142df17294cd7b4f46db9d9ceec651.jpg) Date: 2011-08-22 21:37:18
| | An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors Jack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb+ , Vikram Bhatt, Steven Swanson, and MAdd to Reading ListSource URL: cseweb.ucsd.eduDownload Document from Source Website File Size: 350,64 KBShare Document on Facebook
|