Date: 2012-08-23 22:17:16

Parallel computing

Central processing unit

Computer architecture

Instruction set architectures

Microprocessors

CPU cache

Computer architecture simulator

ARM architecture

Multi-core processor

Speedup

Emulator

Microcode

Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator Zhenman Fang1,2 , Qinghao Min2 , Keyong Zhou2 , Yi Lu2 , Yibin Hu2 , Weihua Zhang2 , Haibo Chen3 , Jian Li4 , Binyu Zang2 1 The State Key Lab of ASIC &

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