IBM / Schlumberger / NEC / Stellar Computer Inc. / Texas Instruments / /
Facility
Pixel Processors Backing Store / Computer Science University of North Carolina Chapel Hill / I/O port / Carleton College / /
IndustryTerm
Host communications / little hardware / large computing surface / algorithm developer / speed rendering hardware / pixel processing / 2D computing surface / communication protocol / interactive graphics systems / gigabit ring network / capable communications network / particular rendering algorithm / raster graphics systems / memory devices / pixel processing elements / pixel processor / external processing / processor-enhanced memory chips / real-time interactive applications / primitive processing / graphics algorithms / compact pixel processors / logic-enhanced memory chip / computer applications / graphics processors / speed digital systems / pixel processors / performance network / memory chips / 3D medical imaging / designated graphics processor / parallel processors / bits/pixel on-chip / real-time algorithm research / graphics systems / image-processing algorithms / on-chip / communications to/from / client processor / real-time systems / 2D applications / /
OperatingSystem
UNIX / /
Organization
Defense Advanced Research Projects Agency / office of Naval Research / National Science Foundation / University of North Carolina / Computer Science University / Laura Israel Department / Department of Mathematics / DARPA ISTO Order / Carleton College / /
Person
John Eyles / David Ellsworth / Henry Fuchs / Pixel / Brice Tebbs / Greg Turk / Ring Node / John Poulton / Steve Molnar / J. William Poduska / /
A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories1 Henry Fuchs, John Poulton, John Eyles, Trey Greer, Jack Goldfeather2, David Ellsworth, Steve Molnar, Greg Turk, Brice Tebbs, Laura Israel