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Digital electronics / Electrical circuits / Electronic design / Computer memory / Asynchronous circuit / Clock signal / Delay insensitive circuit / Flip-flop / Quasi Delay Insensitive / Electronic engineering / Electrical engineering / Electronics


Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding
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Document Date: 2006-02-13 13:52:04

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File Size: 115,68 KB

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City

Cambridge / Dordrecht / /

Company

TSMC / VLSI Systems / /

Country

Netherlands / United Kingdom / /

/

Event

FDA Phase / Bankruptcy / /

Facility

Electrical Engineering Systems University of Southern California Los Angeles / STFB pipeline / California Institute of Technology / /

IndustryTerm

manufacturing technology scales / /

Organization

California Institute of Technology / Peter A. Beerel Department / Cambridge Univ. / Electrical Engineering Systems University of Southern California Los Angeles / /

Person

P. A. Beerel / V / V.I. Varshavsky / Introduction / Peter A. Beerel / Marcos Ferretti / /

Position

editor / datapath designer / /

Product

M-16 / R1 / /

ProvinceOrState

Utah / California / /

PublishedMedium

Communications of the ACM / /

Region

Southern California / /

Technology

four-phase protocols / four-phase protocol / simulation / typical four-phase protocol / /

SocialTag