San Francisco / Santa Clara / Rochester / Anaheim / Austin / Washington / DC / New Orleans / Huntington Beach / San Diego / San Jose / /
Company
LSI / Artisan Taiwan Semiconductor Manufacturing Company / Authorized / Synopsys / Texas Instruments / SVT-SGL I S A / IEEE Authorized / STMicroelectronics / Intel / Low Power Electronics / /
Country
United States / /
Currency
USD / / /
Facility
LGate library / LIBRARY TABLE V IMPACT OF GATE / University of Michigan / University of California / /
IndustryTerm
nominal devices / digital signal processor / mobile multimedia applications / manufacturing yield / deep submicron silicon semiconductor manufacturing / nominal and biased devices / manufacturing processes / manufacturing process / metal / noncritical devices / power applications / technology level / technology nodes / wireless applications / heuristic algorithm / microprocessor chips / potential manufacturing / nano-scale technologies / optimization tool / technology scaling / reticle enhancement technology / manufacturing / active devices / speed digital circuit technology / /
OperatingSystem
ECOs / /
Organization
University of Michigan / Ann Arbor / Univ of Calif Los Angeles / Department of Electrical Engineering and Computer Science / Department of Computer Science and Engineering / University of California at San Diego / ASIC / Department of Electrical and Computer Engineering / /
Person
S. Sapatnekar / P. Sharma / C. Oh / Y. Cao / J. Zuo / K. Schroder / P. Gupta / A. B. Kahng / S. Sirichotiyakul / R. Panda / A. Dharchoudhury / D. Blaauw / D. Sylvester / A. Srivastava / J. Yang / Dennis Sylvester / R. Rao / T. Edwards / Andrew B. Kahng / /
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 8, AUGUST[removed]Gate-Length Biasing for Runtime-Leakage Control Puneet Gupta, Student Member, IEEE, Andrew B. Kahng, Member