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Digital electronics / Electronic engineering / Electronic design automation / Electrical engineering / Clock signal / Digital systems / Clock gating / Energy conservation / Gating / Clock / Flip-flop / Power optimization


IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRILDesign Flow for Flip-Flop Grouping in Data-Driven Clock Gating
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Document Date: 2014-03-31 16:24:12


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File Size: 833,84 KB

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