| Document Date: 2009-01-24 12:41:00
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Company Vcache / RTL / IEEE Authorized / Authorized / Intel Corporation / / Currency USD / / / Facility duplex FBD2 / North Carolina State University / Fort Collins / / IndustryTerm clock distribution network / adjacent metal layers / nm product / directory-based cache coherence protocol / manufacturing hooks / process technology / manufacturing test time / metal option / pull-down device / manufacturing flow / port crossbar router / static state retention device / crossbar router / nm processor / test applications / manufacturing process / inter-processor communications / / OperatingSystem L3 / / Organization US Federal Reserve / North Carolina State University / / Person Brian Cherkauer / Dan Krueger / Mike Gowan / Erin Francom / Charles Morganti / Chris Bostak / Paul Gronowski / Dave Bradley / / Position system utilities controller / QR controller / central di/dt controller / representative / analog driver / memory controller / controller / / ProgrammingLanguage DC / / ProvinceOrState Manitoba / / Technology Itanium processor / 65-nm process technology / full-duplex / 90 nm processor / This processor / Tukwila processor / 12-port crossbar router / directory-based cache coherence protocol / The processor / SRAM / simulation / Digital Object Identifier / V. PBOX This processor / Flash / 12 port crossbar router / /
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18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009