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Digital media / Synchronous dynamic random-access memory / Dynamic random-access memory / Memory controller / Double data rate / CPU cache / Random-access memory / Flash memory / DDR SDRAM / Computer memory / Computer hardware / Computing


PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT
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Document Date: 2008-09-11 03:37:35

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File Size: 475,39 KB

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Company

Channel Selector Bank / Segment Bank / /RAS Command Decoder /CS Bank / Buffer Segment Segment Segment Segment Bank / NEC / NC Bank / /

Country

Japan / /

IndustryTerm

Internet Server etc / command protocol / bank operations / memory core technology / internal banks / memory systems / bank / /

NaturalFeature

Organization Clock Read Prefetch Channel / /

Organization

NC NC / NS CP / /

Position

system memory controller / representative for availability and additional information / /

Technology

VCMemory technology / SDRAM / Flash Memory / same command protocol / INTEGRATED CIRCUIT / /

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