Any Asymmetric / Intel / Any Asymmetric Fence Group / /
Country
Turkey / /
Currency
pence / USD / / /
Facility
Fence Stall / Josep Torrellas University of Illinois / Watchlist stall / Stony Brook University / Other Stall / /
IndustryTerm
fence / software module / software routines / coherence protocol / software transactional memory / fence groups / bank / mesh network / runtime systems / lock-free mutualexclusion algorithm / work-stealing algorithm / wF-only groups / /
NaturalFeature
Performance Comparison Forest / /
Organization
National Science Foundation / PA PA / Stony Brook University / PS GRT / University of Illinois / Department of Computer Science / Illinois-Intel Parallelism Center / /
Person
Wee Counter / Wee heat / Wee knapsack / Wee List / Wee fft / Wee Tree / Wee Hash / Wee lu / Wee cilksort / Wee plu / Wee matmul / Wee fib / Wee ReadWriteN / Wee TreeOverwrite / Stream Architectures (Multiprocessors) / Nima Honarmand / All Fences / Wee cholesky / Wee bucket / / /
Position
cache controller / single writer / concurrent writer / per-core 128KB WB / RT / Head Head / head / writer / .writer / entries Private 32KB WB / programmer / /
Asymmetric Memory Fences: Optimizing Both Performance and Implementability ∗ Yuelu Duan, Nima Honarmand, † and Josep Torrellas University of Illinois at Urbana-Champaign {duan11,torrella}@illinois.edu nhonarmand@cs.s